The present invention relates to a mask data generating method and a mask for an electron beam exposure system, particularly an electron beam exposure system of the type exposing a plurality of desired patterns collectively in a large scale memory or similar semiconductor integrated circuit (IC).
Today, even patterns as fine as 0.2 .mu.m to 0.3 .mu.m or so are applied to semiconductor IC quantity production lines. In parallel with the decreasing pattern size, not only photolithography using ultraviolet rays and X-ray lithography using X-rays but also electron beam lithography using an electron beam are attracting increasing attention. However, a known electron beam exposure system has a problem that the throughput is far lower than the throughput available with an optical aligner using a stepper, as taught in "High Throughput Electron Beam Lithography System", Hitachi Review, Vol. 76, No. 7 (1994-7). A simultaneous electron beam exposing method is capable of improving the minimum fabricating dimensions and enhancing the throughput. This kind of exposing method uses a mask for an electron beam exposure system is formed with a desired pattern beforehand. The mask promotes efficient exposure especially when a number of identical patterns are sequentially exposed like the memory cells of a large scale memory.
It is a common practice with the simultaneous electron beam exposing method to produce a mask formed with a desired pattern in the from of an aperture. The mask is located in the vicinity of the optical axis of an electron beam. An electron beam is radiated via the aperture in order to transfer the desired pattern to a silicon (Si) wafer. To increase the throughput of an exposure system, it has been customary to determine the size of the aperture on the basis of, among various repeated pattern areas included in design data, the size of a repeated pattern area closest to the maximum shot or radiation area.
Japanese Patent Laid-Open Publication No. 5-343304, for example, discloses a method of extracting out of design data a repeated pattern having the maximum size applicable to a partial simultaneous electron beam exposure system. This method implements efficient extraction by executing the extraction with consecutive mask patterns in parallel. However, the problem is that a repeated pattern closest in size to the largest area which a partial simultaneous electron beam exposure system can shoot is simply extracted. Specifically, assume that this method is applied to, e.g., a device separation pattern or a capacity pattern of a DRAM (Dynamic Random Access Memory). Then, even when the desired pattern is smaller in size than the maximum shot, patterns extending over the boundary between nearby shots is divided. By the division, a mask pattern for the exposure system is extracted. Assume that the above mask pattern is used to produce a mask for the exposure system and then effect partial simultaneous electron beam exposure. Then, connection errors occur at each time of exposure, due to the deviations of the patterns divided on the boundaries of the repeated pattern areas. Consequently, resist patterns transferred from the mask to the wafer are low in dimensional accuracy. Moreover, because the matching of the repeated patterns must be taken into consideration, the mask pattern extracting procedure is complicated.
There is an increasing demand for dimensional accuracy of less than .+-.0.02 .mu.m for a designed pattern dimension of 0.2 .mu.m in order to implement high integration and fine configuration of devices. It is therefore necessary to reduce the deterioration of dimensional accuracy ascribable to the connection errors discussed above.
Technologies relating to the present invention are also disclosed in. e.g., Japanese Patent Laid-Open Publication No. 5-136036.